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HP2-Q03 - Selling HP Integrity Server Solutions - Dump Information

Vendor : HP
Exam Code : HP2-Q03
Exam Name : Selling HP Integrity Server Solutions
Questions and Answers : 60 Q & A
Updated On : June 14, 2019
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Test Number : HP2-Q03
Test Name : Selling HP Integrity Server Solutions
Vendor Name : HP
Q&A : 60 Dumps Questions

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Selling HP Integrity Server Solutions education

RISC-V business | HP2-Q03 Dumps and Real test Questions with VCE Practice Test

“Don’t seem to be returned. some thing should be would becould very well be gaining on you.” – Satchell Paige

closing week’s RISC-V Tech Symposium, held on the desktop background Museum in Mountain View, had all the spirit of a tent revival assembly, which is appropriate because microprocessor ISA supporters are inclined to sound a lot like non secular zealots. The open-supply RISC-V ISA is not any different during this admire. despite the fact begun for essentially the most grounded of functions – the schooling of future processor designers – the RISC-V ISA is hastily turning out to be far beyond its origins and is bumping along the road to become a full-blown, commercial microprocessor ISA regardless of its open-supply underpinnings. The underwriter of the international sequence of RISC-V Tech Symposiums, SiFive, is one of the loudest cheerleaders for the RISC-V ISA’s trek against commercial relevance and, in all probability, world dominance.

My July 19, 2018 EEJournal article titled “RISC-V goals for World Domination” incorporates a long heritage of microprocessor ISAs. listed here, I quoted Dr. David Patterson, the professorial godfather of RISC-V, who mentioned: “Why should there be open-supply compilers however no longer open-supply ISAs?” That article quoted Patterson as he mentioned the thought that the open RISC-V ISA is usually a treatment to microprocessor ISAs’ hacking vulnerability. The quote came from a presentation Patterson made on the 2018 annual dinner assembly of the IEEE-CNSV (IEEE Consultants’ community of Silicon Valley). Patterson concluded that presentation with a simple commentary about RISC-V: “That’s my essential intention for RISC-V: world domination.”

fast ahead half a year to this month’s RISC-V Tech Symposium at the desktop background Museum. several hundred individuals attended, and they didn’t come just for the bagels and fruit. They got here to hear about the new ISA faith. besides the fact that children they bought lots of that variety of verbiage from the SiFive presenters at the symposium, who promised the world together with an answer to the slowing of Moore’s legislations, attendees got a greater sober and rational look at the state of RISC-V from Martin Fink, who became giving his first presentation as interim CEO of the RISC-V basis. Fink is also the CTO at Western Digital (WD), a position he’s held for simply over two years.

As a reminder, WD introduced late final year that it became establishing a RISC-V processor core (no longer an ISA, an IP core) referred to as SweRV, which the enterprise is putting into the open-supply community. additionally, WD has developed an open-supply, RISC-V instruction-set simulator for the SweRV processor core, and the enterprise has initiated an open regular initiative for cache-coherent reminiscence over a network for use in RISC-V environments. WD is excited by RISC-V. The enterprise’s press announcement about the processor core states, “Western Digital expects each the SweRV Core and SweRV ISS will support to accelerate the business’s stream to an open source guide set structure.”

In other words, WD has purchased into the open-supply RISC-V move bigly, which should now not come as a surprise. WD ships on the order of 1000000000 processor cores per 12 months in its storage products, so an open-source core implementation that WD manages and can pay no royalties to use has received to be pleasing.

right through his keynote at the RISC-V Tech Symposium, Fink recounted a story concerning the first time he met Marc Andreesen. This changed into when Fink was a VP working a “small company unit” at HP. It changed into the enterprise crucial systems community in citadel Collins, Colorado – my ancient HP stomping grounds – which become responsible for HP’s Integrity servers at the time. Andreesen had just joined HP’s Board of administrators. His “tag line” changed into “application is consuming the world.” This tag line “irked the heck out of” Fink, as a result of he considered HP to be a $one hundred billion hardware business, no doubt because he became in charge of HP’s Integrity server line on the time.

Now that he’s the [Interim] CEO of the RISC-V foundation, Fink has revised Andreesen’s tag line for his personal use. He proposed here edition:

“Silicon: The oxygen that allows application to breathe”

So it’s now not all in regards to the software, says Fink. It’s about the symbiotic relationship between hardware and application. possibly here is a transcendental revelation to some americans, but it appears to me that British desktop scientist Maurice Wilkes had the equal vision in the late Nineteen Forties whereas he and his team have been developing the EDSAC and EDVAC programmable computers. Hardware/software co-construction is actually a extremely historical concept in computing. Wilkes and company certainly understood the symbiosis between hardware and utility back then, however silicon had nothing to do with computing at the time. It turned into still the tube period.

in spite of everything, Fink sees the RISC-V circulate as a way to get lower back to the Wilkes’ model of optimizing hardware and utility collectively. in line with Fink, inserting the RISC-V ISA into the palms of the open supply community and modularizing the ISA unlocks the processor architecture and encourages greater innovation.

additional, Fink sees the RISC-V stream as a step faraway from the polarized world of hardware and application nowadays, as if the processor designers at Intel were ignoring the massive overhang of present code. (adequate, they did exactly that after it came to Itanium, see “news Flash: Itanic nonetheless Sinking” and “Itanium Deathwatch eventually Over,” but, in typical, processor designers pay lots of attention to how well application runs on their machines.) as an alternative, Fink says, the RISC-V open-supply stream is more of a win-win circumstance, where hardware and utility each win.

Fink also referred to that there are farsighted construction groups which are optimizing hardware and utility collectively. “That’s why you’re seeing things like [Google’s] TPU chip,” he brought. Google, which has funds to burn, decided that it vital to build a proprietary AI chip above all for laptop studying. Google’s TPU edition three.0 consumes so a good deal vigour that it wants water cooling.

my own tackle Google’s TPU is that no commercial processor dealer is probably going to stay 65,000 multipliers into a multiprocessor chip aimed toward the prevalent market. Few agencies besides Google and governments have that plenty funds to throw at a particular utility difficulty, and not many can find the money for water cooling for his or her gadget designs, so I’m now not satisfied that Google’s TPU represents a pretty good example of co-optimizing hardware and software within the true world where most of us live.

My eight years of journey at Tensilica, where I evangelized proprietary configurable processor cores, taught me that few engineering groups wish to blaze a brand new direction on the ISA panorama. That’s yet another diploma of freedom that they don’t have time to cope with, and most of them don’t consider the deserve to fiddle with ISAs. That’s now not the perceived bottleneck, and never each enterprise has the deep pockets and supplies of a Google (or a WD for that rely).

Let’s get actual, right here. This idea of widespread hardware/software optimization could sound nice, but there are some bedrock, useful, financial barriers being glossed over within the RISC-V zealotry and hype. fortunately, that’s as non secular as Fink bought about RISC-V.

His keynote grew to be extra practical and useful.

“Why RISC-V?” asked Fink. current ISAs are a long time old, he spoke of, and “there are elements in time the place you deserve to make architectural leaps ahead.” The slowing of Moore’s legislations potential that physics is not going to take us forward as fast as it once did. as a substitute, we are able to rely more on architectural advances coupled with software innovation.

adequate, well that’s exceptional. I agree that the relentless journey alongside the Moore’s legislation path has put architectural innovation on the returned burner the place it doesn’t belong. It’s good to seem to be to gadget architecture for the subsequent efficiency leaps, however the RISC-V ISA isn't a progressive step past different RISC ISAs, regardless of the supposed decrepitude of those “decades-ancient” architectures.

From my perspective, the massive RISC-V contribution to our trade is the open-source nature of the ISA. Ecosystem companies can opt for up many IP and silicon vendors through becoming a member of the RISC-V group. Of route, they additionally choose up an immense set of companies by leaping on the Arm Cortex teams, so I don’t see that as a big differentiating aspect for RISC-V – not from my vantage point. additionally, Wave Computing, the latest proprietor of bad historic MIPS, recently announced that it might release the MIPS processor ISA to the open-supply neighborhood through a application known as MIPS Open. I certainly think you may deliver partial credit to the RISC-V move for this turn of events.

Fink, a “server guy” at heart, then burst a couple of bubbles among the RISC-V zealots via announcing:

“if your ambition is to change a Xeon processor with a RISC-V processor in a server, simply stop right there. That should still not be your ambition. That should still now not be what you wish to go after. There’s no point. You’re not going to get any place doing that.”

“however that you can rethink the structure of a server,” he continued. “How an awful lot leading memory may still there be in a server? How a lot storage is enabled? What sorts of silicon customizations are you able to make to optimize portions of the workload? where are the hardware/application tradeoffs? That’s for those who get to the magic and the power of what RISC-V can convey.”

again, I strongly believe Fink’s system-stage optimization sentiments, however I’m failing to see the particular nature of the modular RISC-V ISA that can destroy the bottleneck that’s been protecting designers back from the flowering of processor-primarily based ASIC design. My experiences at Tensilica and Cadence tell me that the processor ISA isn't the fundamental bottleneck. The actual limiting factors have become the building funds, the engineering components, the design and verification equipment, and the construction time vital to create an ASIC. opt for any processor core, make it free, and you’ll still discover a ton of limitations within the ASIC-construction route. Even after attending the RISC-V Symposium, I fail to notice how the open-source RISC-V bandwagon fundamentally changes the equation.

Fink persisted: “Rethink the difficulty from the ground up. Don’t [design a system in] a definite manner as a result of that’s how it’s been done for the past 10, 20, 30, 40 years.” (We’re within two and a half years of the microprocessor’s fiftieth birthday, so quickly which you can soon add a further decade to Fink’s listing.) “if you’re going to design your equipment with a new ISA but a crusty historical equipment architecture, your success will be restricted, in case you succeed at all,” he mentioned.

finally getting right down to brass tacks, Fink enumerated his view of the RISC-V advantages:

It’s a modular ISA. The guideline set modules (integer, floating-aspect math, compressed instructions, vector guidance, and so on.) are sturdy and locked in after ratification, which offers mounted targets for ecosystem developers. These locked-in guideline modules deliver builders with a sturdy baseline. next year’s RISC-V processor models will deliver the equal ISA, and any changes can be restrained to new modules proposed by way of others or to proprietary modules that you develop your self. That closing bit is awfully Tensilica-like, and, as I’ve noted above, the concept turned into now not a large seller. although, I do strongly accept as true with that ISA modularity is a “first rate aspect” within the ASIC design sphere.

the usage of WD as an example, Fink reminded the audience that WD is making the SweRV RISC-V IP core attainable to the open-source community. despite the fact, WD intends to enhance proprietary ISA modules with some variety of really expert, custom guidelines for certain storage applications. WD does not plan to share these really good guidelines with the open-supply group. This method permits WD to leverage the starting to be ecosystem for the standardized RISC-V platform whereas still permitting it to strengthen and leverage personalized processors for a competitive facet.

the liberty to take this route sounds very nice in concept, but, as Fink pointed out, WD will then should manage the construction-device chain for these really expert processors, as a result of they'll have deviated from the usual ISA modules that the typical RISC-V ecosystem helps. From event, i do know that small building groups would like to develop really good ASICs with architectures tailored to particular applications, but lots of these companies not huge enough to shoulder the burden of managing personalized tool chains.

once more referencing my days as a Tensilica evangelist and channeling my inner Yogi Berra, the RISC-V bandwagon is like déjà vu in every single place once again.


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