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650-756 - Advanced IP NGN Architecture Field(R) Engineer - Dump Information

Vendor : Cisco
Exam Code : 650-756
Exam Name : Advanced IP NGN Architecture Field(R) Engineer
Questions and Answers : 60 Q & A
Updated On : February 15, 2019
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650-756 Advanced IP NGN Architecture Field(R) Engineer

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650-756 exam Dumps Source : Advanced IP NGN Architecture Field(R) Engineer

Test Code : 650-756
Test Name : Advanced IP NGN Architecture Field(R) Engineer
Vendor Name : Cisco
Q&A : 60 Real Questions

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Cisco Advanced IP NGN Architecture

Cisco launches carrier issuer know-how specializations | killexams.com Real Questions and Pass4sure dumps

keeping its word to extend its cyber web of things (IoT) specializations, Cisco nowadays announced a suite of carrier issuer know-how specializations for partners drawn to expanding into new enterprise opportunities.

the brand new service company specializations are designed to position Cisco companions to monetize on the starting to be IoT market, projected to be price $19 trillion in 10 years, in line with Steve Benvenuto, senior director of company construction for Cisco’s international associate company, at the launch of the supplier’s first IoT specializations in November.

the brand new 4 provider provider expertise specializations are superior carrier issuer Routing know-how Specialization, advanced provider provider Mobility technology Specialization, superior provider company Optical expertise Specialization and advanced provider provider structure Specialization.

The superior carrier issuer Routing expertise Specialization makes a speciality of router solutions, in particular abilities in carrier provider core, part and entry routing applied sciences; optimization solutions; and application-defined networking (SDN).

The advanced carrier issuer Mobility technology Specialization practising will permit partners to sell new generations of mobile, small-telephone and service issuer Wi-Fi.

the brand new advanced service issuer Optical technology Specialization makes a speciality of optical solutions and how to present packet switching, optical transport network (OTN), and Cisco Dense Wave Division Multiplexing (DWDN) and IP over optical convergence items. The specialization additionally teaches companions the way to work with Cisco network Convergence device (NCS) 2000 and 4000 collection routers.

With the superior service provider architecture Specialization, companions will learn about service company routing applied sciences together with both carrier provider mobility or provider issuer optical technologies.

in keeping with Cisco, the brand new suite of service provider expertise specializations represents the enterprise’s next technology of the advanced IP next-technology community (IP NGN) structure Specialization and the cell information superhighway technology (MIT) authorized technology provider (ATP) designation, which will be retired beginning in March 2015.

the brand new service issuer expertise specializations are at the moment purchasable with extra application updates anticipated in 2015.


Suraj Shetty | killexams.com Real Questions and Pass4sure dumps

Vice PresidentWorldwide provider issuer advertising

Suraj Shetty is the vp of advertising and marketing for the Cisco worldwide provider provider advertising company and leads a number of teams chargeable for using provider issuer success in development and deployment of advanced services based on Cisco items and options. His important areas of focus consist of enabling service suppliers to radically change into experience suppliers through the Cisco IP next generation network (IP NGN) architecture and convey prosperous related existence experiences. Shetty is additionally focused on the acceleration of advanced IP applied sciences throughout the foreign Telecommunication Union (ITU), the web Engineering task drive (IETF), and different industry requisites bodies.

Shetty is a everyday speaker at industry movements and symposia and is a foremost Cisco spokesperson to press in addition to each business and economic analysts.

Shetty has held many product management and advertising and marketing roles in his 11 years at Cisco, including two-tier distribution channel advertising, product advertising for DSL-related items and options, and the Cisco Broadband Aggregation solution portfolio. prior to his present position, Shetty served as director of advertising in the Cisco provider issuer Routing know-how neighborhood with responsibility for carrier provider core and aspect routing products.

prior to becoming a member of Cisco, Shetty changed into a Senior Engineering advisor at Eicon expertise, focused on systems network architecture (SNA) gateway and routing options. Shetty holds a M.S. diploma in electrical engineering from the tuition of Texas at San Antonio, and a bachelor of engineering diploma in electronics and communications from Karnatak school in India. He lives in San Jose along with his spouse and two infants.

XO Communications hurries up construction and delivery of IP subsequent-generation community functions With Cisco | killexams.com Real Questions and Pass4sure dumps

supply: XO Communications

February 26, 2008 08:00 ET

Collaboration Strengthens XO's IP Portfolio and commercial enterprise services Capabilities

HERNDON, VA--(Marketwire - February 26, 2008) - XO Communications (OTCBB: XOHO), a number one company of twenty first century communications for businesses and communications provider providers, today announced a 3-yr settlement with Cisco® to speed up the construction and delivery of next-generation Cisco Powered IP communications capabilities for agencies and large organizations via collaboration on features and solutions as well as joint advertising and revenue initiatives.

the two corporations will combine leading-facet networking applied sciences from Cisco with XO's nationwide transport and IP networking capabilities to focal point on the transforming into demand for IP convergence and networking services. in addition, the contract will support XO Communications accelerate the development of recent capabilities under the XO IPfolio and strengthens the business's go-to-market capabilities as it expands its presence in the enterprise market.

NEW Cisco Powered carrier Designations

XO Communications has also obtained the Cisco Powered provider designation for a couple of services, including MPLS IP-VPN, Metro Ethernet, protection, internet internet hosting and committed cyber web access. These designations show to groups and big businesses that XO Communications has committed to investing in the components, programs, and methods to install, manage, and support extraordinary managed IP and networking features.

"XO and Cisco share a vision for the proliferation of managed features to permit company customers to center of attention on their core capabilities in preference to their IT infrastructure," stated Jeff Spagnola, vice president provider provider advertising at Cisco. "XO is a pacesetter in the market in constructing out its service portfolio, with a purpose to allow its existing and future valued clientele to increase productiveness while reducing the capex and opex linked to internal deployment of those elements."

increasing XO's IP services Portfolio

XO Communications has already developed and delivered to market a number of converged and IP networking functions according to the Cisco IP subsequent-generation community (IP NGN) architecture, including XO Metro Ethernet, XO IP Flex, XO SIP, XO VPN and XO MPLS IP-VPN. together, XO Communications and Cisco intend to collaborate on the building of recent Cisco Powered Managed capabilities and options bundles that incorporate new application-aware MPLS IP-VPN, managed security and subsequent generation Unified Communications features so as to present firms more desirable aspects and functionality for his or her mission-important networks.

"With this agreement, XO Communications is taking a management position in delivering new and advanced IP solutions that enable firms to converge voice and information networks for multiplied network performance and employee productiveness," mentioned Tom Cady, president of XO enterprise functions. "by using working intently with Cisco, we're greater located to make the most of Cisco's expertise leadership and distribution channels to bring new IP solutions to the enterprise market promptly."

next-technology community and extended means offers Platform for new IP features

XO Communications will deliver these new services over its advanced, nationwide IP network. XO Communications recently announced a major enlargement in the means of its nationwide IP community in line with the Cisco IP NGN structure. The deployment of the Cisco CRS-1 provider Routing gadget will more than double present ability and units the stage for a 4-fold increase, whereas helping XO Communications meet the becoming demand for top-velocity internet access services and guide its enlargement into the high-capacity IP transit services market.

income Collaboration

companies will additionally improvement from collaboration between XO and Cisco income forces. The managed features, a few of which can be found now and others which are scheduled to be deployed in 2008 and 2009, are designed to help shoppers maximize returns on existing community investments by means of enabling consolidation and improve of multi-provider IP networks. These functions ultimately might be made attainable via direct and indirect earnings channels.

About XO Communications

XO Communications, a subsidiary of XO Holdings, Inc. (OTCBB: XOHO), is a leading issuer of twenty first century communications capabilities for agencies and communications services suppliers, together with 50 % of the Fortune 500 and leading cable groups, carriers, content material providers, and mobile operators. using its pleasing and strong nationwide IP network and wide local metro networks and broadband instant facilities, XO offers valued clientele a wide range of managed voice, statistics and IP capabilities in 75 metropolitan markets throughout the us. For extra counsel, seek advice from www.xo.com.

ahead-searching commentary observe

The statements contained in this free up that aren't ancient information are "ahead-searching statements" (as such term is described within the deepest Securities Litigation Reform Act of 1995) that contain hazards and uncertainties. These statements include those describing the advantage from new initiatives and enhancements to XO Communications' business and carrier markets, XO Communications' means to proceed boom in facts and IP features, its ability to extend market share through IP and private networking initiatives, and XO Communications' capacity to benefit from improved network capacity and extra features from its lengthy haul community. management cautions the reader that these forward-looking statements are handiest predictions and are field to a number of both ordinary and unknown risks and uncertainties, and specific effects, performance, and/or achievements of XO Communications can also vary materially from the future consequences, efficiency, and/or achievements expressed or implied via these forward-looking statements on account of a couple of factors. These elements consist of, with out trouble, our capacity to generate adequate capital or to achieve financing. management is unable to provide assurance that XO Holdings, Inc. or its subsidiaries will ultimately consummate option financing transactions or that such financing transactions may be consummated earlier than the lenders beneath our credit score Facility could speed up reimbursement of the miraculous indebtedness. other factors to believe additionally consist of the chance elements described on occasion in the studies filed by using XO Holdings, Inc. with the Securities and exchange commission, including its Annual report on kind 10-k for the year ended December 31, 2006 and its quarterly reviews on form 10-Q. XO Holdings, Inc. undertakes no duty to update any forward-searching statements.


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Advanced IP NGN Architecture Field(R) Engineer

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Sprint First U.S.-Based Global Communications Provider to Achieve Cisco TelePresence Connection Certification | killexams.com real questions and Pass4sure dumps

OVERLAND PARK, Kan., Jun 18, 2007 (BUSINESS WIRE) -- As the first U.S.-based global communications provider to achieve the Cisco TelePresence Connection Certification, Sprint’s (NYSE:S) tier one global IP/MPLS network will provide businesses a high-quality experience when using the Cisco TelePresence Meeting solution.

"Building upon a long history of recognition in delivering customers with strong reliability, flexibility and quality of service through our IP network, Sprint has reached another milestone by becoming the first U.S.-based global provider to achieve Cisco TelePresence Connection Certification," said Barry Tishgart, vice president of converged business solutions for Sprint. "Receiving this certification recognizes the inherent quality of our IP network architecture to support the convergence of real-time voice, video and data over a single IP/MPLS network."

The Cisco TelePresence solution is best delivered over a Cisco-Certified TelePresence network connection, which Sprint is the first U.S.-based global provider to achieve, and takes advantage of Cisco Internet Protocol Next-Generation Network (IP NGN) architecture and innovative technology to deliver a highly scalable and secure solution. The Cisco TelePresence system creates unique, "in-person" experiences between people, places and events in their work and personal lives. It delivers life-size images, ultra-high-definition video (1080p), spatial audio and a specially designed environment to create a "room within a room" meeting space.

The Cisco certification program for TelePresence services provides businesses an added level of confidence that providers such as Sprint can deliver life-like communications experience needed for an optimal TelePresence experience. It provides continual assurance that Sprint’s network maintains its level of quality, conforms to industry and regulatory standards, and meets or exceeds enterprise requirements for operational excellence. The certification process goes beyond static service measurement of network performance. It adds best practices based on current industry standards for network architecture, management and performance including measurement, staff, processes and tools. These are audited annually to help ensure that providers are committed and able to offer an optimal TelePresence experience. For more information, see: https://www.cisco.com/en/US/netsol/ns672/networking_solutions_white_ paper0900aecd805bbda0.shtml (Due to its length, this URL may need to be copied/pasted into your Internet browser’s address field. Remove the extra space if one exists.).

"We are very pleased to announce Sprint as the first U.S.-based global communications provider to achieve the Cisco TelePresence Connection Certification," said Jeffrey Spagnola, vice president of service provider marketing at Cisco. "The Cisco TelePresence Meeting solution enables new collaboration opportunities, but also imposes significant demands on the network. Innovative providers such as Sprint who are delivering TelePresence services must support stringent service-level agreements (SLAs) for quality of service (QoS) and high availability. The Cisco IP NGN architecture, adopted by Sprint as the basis of its IP transformation, addresses these requirements by integrating application, service, and network layers in a single carrier-class system."

This certification is added to network quality assurances confirmed in 2005 when Sprint’s IP/MPLS network received the Cisco IP VPN Multi-Service QoS Certification -- which means the network exceeds Cisco standards for running converged services such as voice, video and data. Sprint was also the first service provider to have demonstrated through a third-party assessment that its MPLS VPN service meets Cisco’s best practices and standards for delivering quality of service (QoS).

Sprint Nextel continues to invest significantly to enhance its wireline network, which has global reach through the company’s powerful IP and MPLS platform. During the 2006 and 2007 time period, Sprint expects to have invested approximately $1.4 billion in its wireline network. This year’s wireline investment is aimed at enhancing MPLS VPN service, voice-over-IP (VoIP) capabilities, IP transport solutions, network footprint/Global IP expansion and increased packet access capabilities such as Ethernet. Investments will also be made to enhance managed network and security services, as well as fixed mobile convergence.

About Sprint Nextel

Sprint Nextel offers a comprehensive range of wireless and wireline communications services bringing the freedom of mobility to consumers, businesses and government users. Sprint Nextel is widely recognized for developing, engineering and deploying innovative technologies, including two robust wireless networks serving 53.6 million customers at the end of the first quarter 2007; industry-leading mobile data services; instant national and international walkie-talkie capabilities; and a global Tier 1 Internet backbone. For more information, visit www.sprint.com.

SOURCE: Sprint

Media Contacts:SprintStephanie Greenwood, 913-794-3658stephanie.greenwood@sprint.com


eSilicon Announces Technical Advisory Board | killexams.com real questions and Pass4sure dumps

SAN JOSE, Calif., Jan 29, 2019 (GLOBE NEWSWIRE via COMTEX) -- SAN JOSE, Calif., Jan. 29, 2019 (GLOBE NEWSWIRE) -- eSilicon, a leading provider of FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions, announced today the formation of a technical advisory board (TAB) focused on guiding the company's development work associated with artificial intelligence ASICS. Members of the TAB include Dr. Dileep Bhandarkar, Dr. Michael Orshansky and Dr. Mattan Erez. The TAB will be led internally by Patrick Soheili.

Dr. Dileep Bhandarkar is an independent datacenter technologies and neural network consultant and is the TAB chairperson. Prior to becoming an independent consultant, Dr. Bhandarkar was the vice president of technology at Qualcomm. Prior to Qualcomm, he was a distinguished engineer at Microsoft and director of architecture at Intel. He has also held positions at Digital Equipment Corporation and Texas Instruments. Dr. Bhandarkar holds a B. Tech. in EE from the Indian Institute of Technology, Bombay and a PhD in EE/Computer Science from Carnegie Mellon University. He is an IEEE fellow.

Dr. Michael Orshansky is a professor and John E. Kasch faculty fellow at the Department of Electrical and Computer Engineering, University of Texas at Austin. Dr. Orshansky received his BS, MS, and PhD degrees in Electrical Engineering and Computer Sciences from the University of California, Berkeley. His recent research is on approximate computing for on-chip machine learning acceleration. Prior to joining UT Austin, he was a research scientist and lecturer with the Department of EECS at UC Berkeley. Prior to moving into academic research, Dr. Orshansky was an early employee at eSilicon. He is an IEEE fellow.

Dr. Mattan Erez is a professor and a Temple Foundation faculty fellow at the Department of Electrical and Computer Engineering at the University of Texas at Austin. His research focuses on improving the performance, efficiency, and scalability of computing systems through advances in memory systems, hardware architecture, software systems, and programming models. His current focus areas are architectures for machine learning, large-scale and high-performance computing, and memory systems. Mattan received a BSc in Electrical Engineering and a BA in Physics from the Technion, Israel Institute of Technology and his MS and PhD in Electrical Engineering from Stanford University.

Patrick Soheili is vice president, business and corporate development at eSilicon Corporation. He is responsible for eSilicon's worldwide business and corporate development activities, with a specific focus on artificial intelligence. Mr. Soheili has been president and CEO of On Demand Microelectronics, Cradle Technologies and Softcoin. He was a founding partner of Barrington Partners, a technology-focused venture capital firm. He has also held positions at Invox Technology, Altera Corporation, AMD and TRW. Mr. Soheili holds a Bachelor of Science in Mathematics from University of California, Santa Barbara and a Masters of Business Administration from Purdue University.

"The artificial intelligence field is rapidly evolving. Deploying ASIC technology to support AI accelerator development presents many challenges," said Patrick Soheili. "The eSilicon neuASIC(TM) platform provides AI-specific IP and an architecture to address these challenges. I welcome the addition of our world-class TAB to help ensure we hit the mark for the dynamic and growing AI field."

To learn more about eSilicon's 7nm neuASIC IP platform or to inquire about access to the platform for design, visit eSilicon's neuASIC web page or contact your eSilicon sales representative directly or via sales@esilicon.com.

About eSiliconeSilicon provides complex FinFET ASICs, market-specific IP platforms and advanced 2.5D packaging solutions. Our ASIC-proven, differentiating IP includes highly configurable 7nm 56G/112G SerDes plus networking-optimized 16/14/7nm FinFET IP platforms featuring HBM2 PHY, TCAM, specialized memory compilers and I/O libraries. Our neuASIC(TM) platform provides AI-specific IP and a modular design methodology to create adaptable, highly efficient AI ASICs. eSilicon serves the high-bandwidth networking, high-performance computing, AI and 5G infrastructure markets. www.esilicon.com

Collaborate. Differentiate. Win.(TM)

eSilicon is a registered trademark, and the eSilicon logo, neuASIC and "Collaborate. Differentiate. Win." are trademarks, of eSilicon Corporation. Other trademarks are the property of their respective owners.

(C) Copyright 2019 GlobeNewswire, Inc. All rights reserved.


More 2.5D/3D, Fan-Out Packages Ahead | killexams.com real questions and Pass4sure dumps

A new wave of 2.5D/3D, fan-out and other advanced IC packages is expected to flood the market over the next year.

The new packages are targeted to address many of the same and challenging applications in the market, such as multi-die integration, memory bandwidth issues and even chip scaling. But the new, advanced IC packages face some technical challenges. And cost remains an issue as advanced packaging is still relatively expensive for the masses.

It’s difficult to list all of the new package types on the horizon, but here are some of the major technologies coming down the pike:

  • 3D-ICs: After years of modest success in developing true 3D packages, the industry is launching a new version of the technology for logic on memory and logic on logic integration. This enables hybrid chip architectures, SRAM cubes and other technologies.
  • Chiplets: With chiplets, you have a menu of modular chips, or chiplets, in a library. Then, you assemble chiplets in a package and connect them using a die-to-die interconnect scheme.
  • Fan-out on substrate packages: These support high bandwidth memory (HBM), while some will break the sub-µm line/space barrier.
  • Each technology is geared toward a different application. Generally, though, the idea behind these and other advanced package types is to integrate multiple die in the same package, which is a form of heterogeneous integration. This, in turn, enables the package to perform a specific and advanced function in a small form factor.

    Heterogeneous integration has other implications, as well. It is becoming an alternative to IC scaling. Packing more transistors on a monolithic IC is becoming more difficult and expensive at each node. Another way to get the benefits of scaling is by putting multiple and advanced chips in an IC package.

    Addressing the ongoing memory bottleneck issues in systems is another driving force behind advanced packaging. In systems, data moves between the processor and memory. But at times this exchange causes latency and power consumption, which is sometimes called the memory wall.

    “The world is driving more data in systems. So, processors need large amounts of memory. And the memory and processor need to be very close,” said Rich Rice, senior vice president of business development at ASE. “So, you need packaging solutions that enable it, whether it’s 2.5D or a fan-out with a substrate approach. This could also be PoP structures like package-on-package. You are putting a mobile memory on top of an application processor, but you are doing it with very dense interconnects.”

    Regardless of the technology, the industry needs to keep a close eye on IC packaging. The overall IC packaging market is projected to reach $68 billion in 2019, up 3.5% over 2018, according to Yole Développement. Of those figures, advanced packaging is projected to grow at 4.3% in 2019, compared to 2.8% for traditional/commodity packaging, according to Yole.

    More 2.5D/3D and chipletsIC packaging is important for several reasons. First, a package encapsulates a chip, preventing it from being damaged. A package also connects the device to a board.

    Second, smartphones and other products require chips with small form factors. This requires small, fine-pitch packages with good electrical performance.

    Third, in some cases, OEMs require a small, multi-die package that performs a specific function, sometimes known as a systems-in-package (SIP). For example, you may need to integrate a communications device with some control circuitry for an IoT or sensing application. “On the SIP front, you are also going to see a lot of heterogeneous integration,” ASE’s Rice said.

    Fourth, customers continue to embrace advance packaging to solve various issues. “Advanced packaging technologies, such as 2.5D, 3D TSV, high-density fan-out, and low-density fan-out, will continue their current courses. We will continue to see incremental improvements in materials, thinness and electrical performance in all sectors of packaging,” said Ron Huemoeller, corporate vice president of R&D at Amkor.

    For years, the industry has been developing advanced packages to address other challenges in systems, such as the memory wall. In today’s memory hierarchy, SRAM is integrated into the processor for cache. DRAM, which is used for main memory, is separate and located in a dual in-line memory module (DIMM). And disk drives and NAND-based solid-state storage drives (SSDs) are used for storage.

    Today’s memory hierarchy has some challenges, especially at the high end. “Customers in AI, machine learning and the data center space are facing challenges where they can’t get enough access to memory. That can be memory on chip or can be memory off chip, off package,” explained David McCann, vice president of post fab development and operations at GlobalFoundries, in a video. “What that is doing for the on-chip memory is driving the die size up. It makes the cost increase.”

    To help solve the problem for high-end applications like servers, the industry is moving toward 2.5D technologies. In 2.5D, dies are stacked on top of an interposer, which incorporates through-silicon vias (TSVs). The interposer acts as the bridge between the chips and a board, which provides more I/Os and bandwidth.

    In one example of a 2.5D package, a vendor could incorporate an FPGA and HBM. Targeted for high-end systems, HBM stacks DRAM dies on top of each other, enabling more I/Os. For example, Samsung’s latest HBM2 technology consists of eight 8Gbit DRAM dies, which are stacked and connected using 5,000 TSVs.

    In total, it enables 307GBps of data bandwidth. In comparison, using conventional DRAM, the maximum bandwidth of four DDR4 DIMMs is 85.2GBps, according to Xilinx. In most versions of 2.5D, the chips are situated side-by-side, although there is some development underway in using “pillars” on top of those chips. But in either case, the memory resides closer to the processor than it would in a classical planar design, and the throughput to external memory is faster.

    “We are addressing the memory latency problem by bringing that memory very close and creating a massively parallel interface between the chips,” McCann said, noting that the downside is that the interposer is relatively expensive. “That adds cost, but it enables us to have dense interconnects between chips.”

    Beyond 2.5D, the next big leap is 3D-ICs or vertical stacking, which promises faster access and lower latency between the memory and processor.

    3D is an overused term that means different things to different people. Some call 2.5D a 3D technology. Technically, a DRAM stack, which has been wire-bonded, is also 3D.

    “Traditionally, 3D-IC means something with a through-silicon via through an active die. People are taking that in different directions,” ASE’s Rice explained. “Then, there are passive interposers. There are also active interposers with some level of circuitry or functionality. You are placing a die on top of that. The interposer is active, meaning that it might have some power circuits or memory.”

    3D-IC technology is not new. It has been in development for years. In 2011, for example, Micron announced the Hybrid Memory Cube (HMC), which stacks memory dies on a logic chip. In 2018, Micron dropped the HMC due to lackluster adoption.

    Another form of 3D-IC is stacking logic dies on each other. “3D logic to logic is not new. There are lots of R&D prototypes from various players, but no production yet,” said Santosh Kumar, an analyst at Yole. “Cost, of course, is the main challenge. But there are technical issues as well, such as thermal management, known-good die, testing and reliability.”

    There appears to be progress on many of these issues, which could finally make 3D-ICs a reality. Vendors now are talking about various products in the arena. For example, GlobalFoundries is developing an “SRAM cube.” Generally, SRAM is integrated with the processor, but SRAM takes up an inordinate amount of real estate. Instead of integrating SRAM with the processor, an SRAM die is stacked on top of the processor and connected with TSVs. The resulting device is an SRAM/logic stack.

    The goal is to shorten the interconnect distance between the processor and SRAM, thereby reducing the latency. “We now have chips that are smaller,” GlobalFoundries’ McCann said. “The overall cost can drop significantly.”

    Beyond that, GlobalFoundries also is developing a combination of 2.5D/3D technology, which promises to enable even faster access to memory. For example, in a 2.5D package, you would place three separate memory stacks on an interposer. The first one is an SRAM cube, which is situated between two HBM stacks on the interposer.

    Meanwhile, Intel recently launched a new 3D packaging technology called “Foveros.” This is not one product, but rather it serves as a technology to enable multi-die packages. It allows chips to be broken up into smaller IP blocks or chiplets, which are connected using an active interposer.

    Intel says it has solved the technical hurdles that have hampered 3D-ICs. “The first thing is solving the two or three intractable problems like thermal and power delivery. It’s a challenge and hasn’t been easily solved. We’ve come up with new innovations to solve that,” said Wilfred Gomes, a senior principal engineer at Intel.

    All told, Intel’s Foveros enables more advanced forms of heterogeneous integration, if not a different way to scale a device. On paper, the technology could match the functionality of an integrated system-on-chip (SOC), according to Intel.

    Intel hasn’t given up on chip scaling, but Foveros provides some new options. For example, using this approach, Intel recently unveiled a new hybrid CPU platform, code-named “Lakefield.” This combines a 10nm processor core with four of Intel’s Atom processor cores into a tiny package.

    Intel and others are paving the way toward the chiplets model. In chiplets, the idea of putting together different modules like LEGOs has been talked about for years, but few have implemented it.

    “The motivation for chiplets is to work in smaller technology increments by either leveraging existing functionality in existing silicon, or creating smaller building blocks that can be mixed and matched as needed for better system optimization, lower costs and faster time-to-market,” said Amin Shokrollahi, chief executive of Kandou Bus. “Chiplets will open a whole new era of silicon innovation and make it easier for smaller players to compete.”

    Kandou Bus has developed an interconnect fabric, which serves as a die-to-die interconnect for chiplets in a package or module. The company is working with several groups in the arena.

    So when will chiplets take off? “Many prototypes have already been built for products that use our Glasswing SerDes technology and we anticipate volume production by middle 2019,” Shokrollahi said. “But broad industry adoption of a chiplet strategy and development of interoperable chiplets is probably still a couple of years away.

    “There are still many questions about how to design, manufacture, assemble and test chiplets and then support these solutions in the field. There are additional challenges when chiplets come from different companies or are manufactured in different foundry processes. Kandou has worked through some of the interface issues, at least from a SerDes perspective, but we definitely see a need for broader industry engagement and cooperation to create a common framework,” Shokrollahi said.

    Yaniv Koppelman, networking CTO at Marvell Semiconductor, agrees. “Today, we are using all kinds of chiplets on switches, and you can populate many types of feeds and speeds with different amounts of chiplets. What we found, though, is the industry is still not ready for this approach technologically. We have not yet hit critical mass. This is why you’re starting to see XSR (extra short-reach), which is an interface from 100-gig PAM-4 that you can shrink. We’re also seeing options for in-package optics, which may drive a standard interface between two chips, although not necessarily in the same company.”

    More fan-outsMeanwhile, momentum is building for another packaging technology called fan-out wafer-level packaging (FOWLP). In fan-out, the dies are packaged while on a wafer. Fan-out doesn’t require an interposer, making it cheaper than 2.5D/3D.

    But packaging customers want HBM, and HBM was only available in 2.5D/3D packages. That is likely to change. The industry currently is working on high-density fan-out packages that integrate and support HBM. These packages could give customers a new and cheaper option for HBM technology.

    With or without HBM, fan-out involves the same basic structure. “In FOWLP, chips are embedded inside epoxy molding compound and then high-density redistribution layers (RDLs) and solder balls are fabricated on the wafer surface to produce a reconstituted wafer,” explained Kim Yess, technology director for the Wafer Level Packaging Materials business unit at Brewer Science, in a blog.

    RDLs are the copper metal connection lines or traces that electrically connect one part of the package to another. RDLs are measured by line and space, which refer to the width and pitch of a metal trace.

    There are three types of fan-out packages—chip-first/face-down; chip-first/face-up; and chip-last or RDL first.

    Initially, fan-out didn’t incorporate a substrate as a base material. At times, though, a substrate-less fan-out package is prone to warpage and/or stress due to a mismatch between the dies and the epoxy mold compound.

    So recently, packaging houses began to develop fan-out on substrate. The flow is similar, but the package uses a BGA substrate, which boosts the reliability of the device. “There are multiple methods to incorporate wafer-based fan-out technologies onto a substrate platform,” Amkor’s Huemoeller. “The use of both low-density and high-density are being employed today depending on die pitch and electrical performance requirements. Both are more typically placed onto current substrates that contain fewer layers with larger features, allowing both reduction in cost and a broader supply chain. These are typically BGA substrates, but HDI boards are being considered.”

    In 2016, for example, ASE introduced a technology called Fan Out Chip on Substrate (FoCoS). Targeted for servers, the first customer for FoCoS incorporated separate 16nm and 28nm dies in the same package. The package has four metal layers with a 2-2.5µm line/space configuration.

    The initial FoCoS package is based on a chip-first flow. Slated for this year, the next-generation FoCoS supports HBM. This version is capable of 2-2µm line/space, with 1.5-2µm due out in the future.

    “ASE is working with customers for a chip-last version of FoCoS, which can support HBM2 memory,” said John Hunt, senior director of engineering at ASE. “It is intended for heterogeneous and homogeneous server applications, as well as AI and chiplet applications. It is intended to be an alternative to an interposer solution for these markets. It provides a lower cost solution, and actually has better electrical and thermal performance than a silicon interposer structure.”

    FoCoS makes use of a BGA substrate. “It is basically the same type of substrate used on a standard BGA package, as well as the same used for a 2.5D interposer package,” Hunt said. “The BGA substrate provides the second level of ‘fan out’ of the package from the finer FoCoS bump pitch to a standard circuit board assembly pitch with an effective cost structure.”

    TSMC, meanwhile, is moving in a similar direction. TSMC’s fan-out packaging technology, called InFO, is being used in Apple’s latest iPhones. Now, the foundry giant is developing a new InFo on substrate technology, dubbed InFO_MS. “InFO_MS is the one that supports HBM,” said Jan Vardaman, president of TechSearch International. “It should be in production this year.”

    “Although InFO_MS is in the early stages of R&D, this technology is meant to integrate HBM onto a substrate directly without an interposer. But it is not easy to achieve this technically,” said Favier Shoo, an analyst at Yole.

    TSMC also is developing an ultra-high density version of InFO, which brings fan-out into the sub-µm regime. Until now, the most advanced fan-out had RDLs down to roughly 2-2µm line/space. However, TSMC is readying InFO at 0.8µm with finer geometries in R&D. “It’s the same architecture. This interconnect density is important for bandwidth improvement. We’ve also minimized the parasitics whenever possible,” said Doug Yu, vice president of R&D at TSMC.

    There are other benefits. “Redistribution layers with smaller critical dimensions enable reducing the total number of redistribution process levels in a fan-out package. This in turn reduces the total packaging cost and improves yield,” said Warren Flack, vice president of worldwide lithography applications at Veeco. “Currently, 1µm RDL is in low volume but we expect that it will increase significantly over the next few years.”

    To pattern the RDL layers in advanced packages, the industry uses various lithographic systems. It’s challenging to pattern the finest RDL features in packages.

    “Most advanced packaging lithography systems are designed for minimum features of 2µm or higher,” Flack said. “Going to smaller features requires exposing with a shorter wavelength and having a larger lens numerical aperture (NA). The major lithography challenges going forward for these advanced fan-out packages are: imaging sub-micron RDL with high-aspect ratios; minimizing overlay errors that occur from die shifting; extremely warped substrate handling; and support for very large 2.5D chip on wafer package sizes. Yield and productivity will drive the cost of adopting advanced fan-out packages. Only very high ASP devices can afford this kind of advanced packaging approach.”

    In fan-out, die shift is one of the bigger problems. During the flow, the dies tend to move in the epoxy material, causing variation and other issues.

    Brewer Science is working on an approach to solve the problem. The technology uses a thin film in a mold compound that works like a stencil.

    Laminated polymetric die-stencil fill concept. Source: Brewer Science

    “Die stencil is an alternative to using the traditional EMC fan-out approach. It doesn’t require the use of a typical EMC in order to create the constituted substrates. It is advantageous because it reduces the warpage commonly observed with EMC fan-out technology and is flexible in integrating all sorts of dies into the package, independent of their sizes and features,” Brewer’s Yess said.

    So going forward, customers will have new and different advanced packaging options on the table. These technologies are impressive, at least on paper. But as before, it’s easier said than done to integrate them in systems, especially at the right price point for demanding customers.

    Related Stories

    Getting Down To Business On Chiplets

    Toward High-End Fan-Outs

    Choosing The Right Interconnect



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    Cisco 650-756 Exam (Advanced IP NGN Architecture Field(R) Engineer) Detailed Information



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